Candidates who are interested to apply MUST be Malaysian citizens and possess relevant requirements as stated.
Qualification Requirements:
Graduates of BSc, MSc or PhD in Electronics/Computer Engineering or equivalent (Minimum CGPA of 3.0 at undergraduate level). The candidate should have strong analytical skills, be able to work independently and work at various levels of abstractions. Any relevant amount of experience in analog circuit design and analysis would be an added advantage.
Additional qualifications (if any) include:
i) Strong background in high speed serial interfaces (>2.5Gb/s), like PCIe2 and SATA2.
ii) High voltage interface in sub-micron process, like DDR, GPIO and HDMI.
iii) Experience in CMOS VLSI analog design, in DLL, PLL and op-amp.
iv) Experience with Very Large Scale Integration (VLSI) circuit layout, and Phased-Locked Loop (PLL) circuit.
v) Experience with UNIX operating environment, cadence design tools, Pearl script, Ocean script.
Candidates who are successful will be expected to perform tasks as stated below:
Tasks Description:
You will be working as a member of the Integrated Circuit (IC) design team developing Hard Intellectual Property (IP) on next generation deep submicron process for the microprocessors and System-On-Chip (SOC) ICs. You will be performing tasks related to VLSI CMOS IC design, solid state physic and physical layout. Such tasks may include: Circuit design of the High speed IO [PCIe, USB3 and DDR], analog integrated circuit design (amplifier and DAC and PLL) and high density CMOS SRAM. You will be performing timing, functional and reliability analysis and supervise physical layout designers. You will be providing support for Full-Chip Pre-Silicon and Post-Silicon Validation, System Validation, Product Test, and Quality and Reliability Engineering to ensure the implementation of feature sets in the final product.
Kindly submit all applications before 30th June 2009 via email to:
BeliaKU_Mahir@ncer.com.my